Silicon oxide layers are commonly used as insulation layers in gate structures of semiconductor devices. In a dynamic random access memory (DRAM) device, for example, silicon oxide may be used for a gate insulation layer, and in a flash memory device, silicon oxide may be used for a tunnel insulation layer.
A thermal oxidation process may be performed on a substrate including silicon to form a gate insulation layer including silicon oxide. When the gate insulation layer is formed, some of the outermost electrons of silicon atoms included in the gate insulation layer may not combine with each other, and thus dangling bonds may occur. The dangling bonds may trap other electrons so that the electrical characteristics, such as transistor threshold voltage and swing characteristics, may be degenerated.
In order to improve the electrical characteristics of the transistor by curing the dangling bonds, an alloy process may be performed. Particularly, after forming a transistor including a gate structure on a substrate, a metal wiring may be formed. A heat treatment process may be performed on the substrate having the transistor and the metal wiring at a temperature of about 400° C. for about 3 hours in an atmosphere of hydrogen gas. In this manner, dangling bonds formed on the gate insulation layer may be transformed into Si—H bonds.
As the degree of integration and operation speed of semiconductor devices have increased, the lengths of wiring formed in the semiconductor devices have generally increased. Due to the increased lengths of the wiring, the total resistance thereof has generally increased and, thus, the resistance-capacitance (RC) delay may be also increased. In order to reduce such problems, copper may be used for the wiring instead of aluminum.
However, when copper is used for wiring, an alloy process used to form the wiring may not cure dangling bonds. In particular, because the copper wiring may be formed by a damascene process, a silicon nitride layer serving as an etch stop layer in the damascene process may absorb hydrogen atoms so that movement of hydrogen atoms to the gate structure may be reduced.
FIG. 1 is a graph illustrating the amount of hydrogen atoms reaching a gate insulation layer for cases in which a silicon nitride layer is formed or not formed. Particularly, FIG. 1 shows the amount of hydrogen atoms included in the gate insulation layer after performing a heat treatment process on a gate structure in an atmosphere of hydrogen gas, when a silicon nitride layer is not formed on the gate structure (A) and when a silicon nitride layer is formed on the gate structure (B). Referring to FIG. 1, the amount of hydrogen atoms included in the gate insulation layer when a silicon nitride layer is formed (B) is much less than that when a silicon nitride layer is not formed (A).
Additionally, when an alloy process is performed after forming the copper wiring, copper ions of the copper wiring may move to neighboring insulation regions so that the reliability of the copper wiring may be degenerated. Furthermore, during an alloy process, gases may leak from a low-k dielectric layer serving as the insulation layer between the copper wiring, so that the semiconductor device may be degenerated.